Doç. Dr. Engin AFACAN
Elektronik Mühendisliği

Engin AFACAN
Telefon
(262) 605 33 16
E-Posta
enginafacangtu.edu.tr
Web sayfası
https://www.gtu.edu.tr/tr/personel/350/39283711/display.aspx
Ofis
A2 Blok, 142
Çalışma alanları
Analog/RF/Mixed IC design, CAD, EDA, Circuit Sizing, Simulation Tools, Variability- and Reliability-Aware Circuit Design and Optimization, Aging in CMOS, Evolutionary Algorithms, VLSI, SNNs.
Detaylı özgeçmiş
Resume.pdf

INTERNATIONAL JOURNAL PUBLICATIONS-SCI INDEXED

İslamoğlu, G., Çakıcı, T. O., Güzelhan, Ş. N., Afacan, E., & Dündar, G. (2021). Deep learning aided efficient yield analysis for multi-objective analog integrated circuit synthesisIntegration,81, 322-330.

Afacan, E., Lourenço, N., Martins, R., & Dündar, G. (2021). Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test.Integration.

Afacan, E. (2020). An efficient reliability simulation tool for lifetime-aware analog circuit synthesis.Turkish Journal of Electrical Engineering & Computer Sciences,28(4).

Afacan, E. (2019). Inversion coefficient optimization based analog/RF circuit design automation. Microelectronics Journal,83, 86-93.

Afacan, E., Dündar, G., Başkaya, F., Pusane, A. E., & Yelten, M. B. (2019). On chip reconfigurable CMOS analog circuit design and automation against aging phenomena: Sense and react.ACM Transactions on Design Automation of Electronic Systems (TODAES);24(4), 1-22.

Afacan, E., & Dundar, G. (2019). A comprehensive analysis on differential cross-coupled CMOS LC oscillators via multi-objective optimization. Integration,67, 162-169.

Aytar, O., Tangel, A., & Afacan, E. (2017). A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology. Journal of Electrical Engineering,68(6), 415.

Afacan, E., Dundar, G., Pusane, A. E., Yelten, M. B., & Baskaya, F. (2017). Aging signature properties and an efficient signature determination tool for online monitoring. Integration,58, 496-503.

Afacan, E., Berkol, G., Dundar, G., Pusane, A. E., & Baskaya, F. (2016). A lifetime-aware analog circuit sizing tool. Integration,55, 349-356.

Afacan, E., Berkol, G., Dundar, G., Pusane, A. E., & Baskaya, F. (2016). An analog circuit synthesis tool based on efficient and reliable yield estimation. </span>Microelectronics Journal,54, 14-22.

Afacan, Engin, Gunhan Dundar, and Faik Baskaya. (2014). Reliability assessment of CMOS differential cross-coupled LC oscillators and a novel on chip self-healing approach against aging phenomena. Microelectronics Reliability 54.2 : 397-403.

OTHER JOURNAL PUBLICATIONS

E.Afacan Low Power High Gain Bulk Driven 3 Stages CMOS Miller OTA in 130nm Technology. Sakarya
Universitesi Fen Bilimleri Enstitusu Dergisi. 2020 Oct 1;24(5):1113-26.

INTERNATIONAL CONFERENCE PUBLICATIONS

Afacan, E. (2021, July). Step Size Determination Approach for Aging Simulations in Analog ICs. In SMACD/PRIME 2021; International Conference on SMACD and 16th Conference on PRIME&(pp. 1-4). VDE.


Spyrou T, El-Sayed S, Afacan E, Camuñas-Mesa L, Linares-Barranco B, Stratigopoulos HG. Neuron Fault Tolerance in Spiking Neural Networks. In 2021 Design, Automation & Test in Europe Conference; Exhibition (DATE), 2021. IEEE.


El-Sayed SA, Spyrou T, Pavlidis A, Afacan E, Camuñas-Mesa LA, Linares-Barranco B, Stratigopoulos HG. Spiking Neuron Hardware-Level Fault Modeling. In 2020 26th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2020. IEEE.


Çakıcı TO, İslamoğlu G, Güzelhan ŞN, Afacan E, Dündar G. Improving POF Quality in Multi Objective Optimization of Analog ICs via Deep Learning. In 2020 European Conference on Circuit Theory and Design (ECCTD), 2020. IEEE.

Afacan E, Berkol G, Dündar G. Post-silicon validation of yield-aware analog circuit synthesis. In2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2019. IEEE.


İslamoğlu G, Çakici TO, Afacan E, Dündar G. Artificial neural network assisted analog IC sizing tool. In 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2019. IEEE.


Lourenço N, Afacan E, Martins R, Passos F, Canelas A, Póvoa R, Horta N, Dundar G. Using polynomial regression and artificial neural networks for reusable analog ic sizing. In 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2019. IEEE.


Kaya E, Afacan E, Dündar G. An Analog/RF Circuit Synthesis and Design Assistant Tool for Analog IP: DATA-IP. In 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, 2018. IEEE.


Afacan E, Dündar G. Design Space Exploration of CMOS Cross-Coupled LC Oscillators via RF Circuit Synthesis. In 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, 2018.IEEE.


Afacan E, Avci YE, Demirbas OO., Variability Analysis Tool for CMOS Analog/RF Circuits: VariAnT, 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, 2018, IEEE.


Odabasi IC, Yelten MB, Afacan E, Baskaya F, Pusane AE, Dundar G. A Rare Event Based Yield Estimation Methodology for Analog Circuits. In 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2018. IEEE.


Afacan E, Ozanoglu K, Toka M. Aging aware safe operating area investigation of switching converter output stages through 2D plots. In2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017. IEEE.


Afacan E, Dündar G. Inversion coefficient optimization assisted analog circuit sizing tool. In2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017. IEEE.


Afacan, E., Dündar, G., and Yelten, M.B. Review: Analog Design Methodologies for Reliability in Nanoscale CMOS Circuits. In 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2017. IEEE.


Afacan, E. Review: Analog Circuit Design Automation Against Process Variations and Aging Phenomena. In Design, Automation, Test in Europe (DATE), 2017 International Conference on. IEEE.


Berkol G, Afacan E, Dündar G, Fernandez EV. A hierarchical design automation concept for analog circuits. In2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2016. IEEE.


Afacan, E., Dundar, G. , Pusane, A. E. , Baskaya, F, and Yelten, B. M. (2016, June). Efficient Signature Selection Tool for Sense and React Systems. In International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2016. IEEE. (Best Paper Runner-up Award)


Afacan, E., Dundar, G., Pusane, A. E., and Baskaya, F. Semi-Empirical Aging Model Development Via Accelerated Aging Test. In International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2016. IEEE.


Afacan, E. and Dundar, A Mixed Domain Sizing Approach for RF Circuit Synthesis, International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS, 2016. IEEE.


Afacan, E., Berkol, G., Dundar, G., Pusane, A. E., and Baskaya, F., A deterministic aging simulator and an analog circuit sizing tool robust to aging phenomena. In International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015. IEEE.


Berkol, G., Unutulmaz, A., Afacan, E., Dundar, G., Fernandez, F. V., Pusane, A. E., and Baskaya, F. . A two-step layout-in-the-loop design automation tool. In IEEE 13th International New Circuits and Systems Conference (NEWCAS), 2015. IEEE.


Berkol, G., Afacan, E., Dundar, G., Pusane, A. E., and Baskaya, F., A novel yield aware multi-objective analog circuit optimization tool. In International Symposium on Circuits and Systems (ISCAS), 2015. IEEE.


Afacan, E., Berkol, G., Pusane, A. E., Dundar, G., and Baskaya, F., A hybrid Quasi Monte Carlo method for yield aware analog circuit sizing tool. In Proceedings of the 2015 Design, Automation, Test in Europe Conference and Exhibition, 2015. IEEE.


Afacan, E., Berkol, G., Pusane, A. E., Dundar, G., and Baskaya, F., Adaptive sized quasi-monte carlo based yield aware analog circuit optimization tool. In 5th European Workshop on CMOS Variability (VARI), 2014. IEEE.


Afacan, E., Berkol, G., Baskaya, F., and Dundar, G., Sensitivity based methodologies for process variation aware analog ic optimization. In Microelectronics and Electronics (PRIME), 10th Conference on Ph. D. Research in, 2014. IEEE.


Chang, D., Ozev, S., Bakkaloglu, B., Kiaei, S., Afacan, E., and Dundar, G. (2014, April). Reliability enhancement using in- eld monitoring and recovery for RF circuits. In IEEE 32nd VLSI Test Symposium (VTS), 2014. IEEE.


Afacan, E.., Ay, S., Fernandez, F. V., Dundar, G., and Baskaya, F., Model based hierarchical optimization strategies for analog design automation. In Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014. IEEE.


Tangel, A., Yakut, M., Afacan, E., and Guvenc, U., An FPGA-based multipleoutput PWM pulse generator for ultrasonic cleaning machines. In Applied Electronics (AE), 2010 International Conference on, 2010. IEEE.


Afacan, E., Aytar, O., and Tangel, A., A High Speed Low-Power CMOS Current Comparator. In IEEJ International Analog VLSI Workshop, International Analog VLSI Workshop, 2008.

NATIONAL CONFERENCE PUBLICATIONS

E. Afacan, Aytar, O., and Tangel, A. "Yuksek Hizli CMOS Akim Karsilastirici" 12. Elektrik, Elektronik, Bilgisayar Muhendisligi 12. Ulusal Kongresi, 2008.

  • Doktora: 2016-Boğaziçi University
  • Yüksek lisans: 2011-Boğaziçi University
  • Lisans: 2008-Kocaeli University
2020-2021 Post-doctorate researcher at Laboratoire d'Informatique de Paris 6, Sorbonne University, Paris, FRANCE.
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